Switch ASICs: Trident, Tomahawk and Silicon One

Two switches can advertise identical port counts, identical speeds and the same rack unit, and behave completely differently under load, because the silicon inside determines buffer depth, telemetry granularity, programmability and power. Understanding the ASIC families is what allows a specification sheet to be read as an engineering document rather than a marketing one.

The major families and what they optimise for

The reasoning behind each family follows from where it sits. Hyperscalers use Tomahawk-class devices in the main fabric where oversubscription must be minimal; Trident-class devices at the edge where feature flexibility matters more than raw bandwidth; and deep-buffer Jericho-class devices where the network has to absorb long bursts or many routes - for example in regional interconnects. Cisco's Silicon One is unusual in aiming for one architecture across routing and switching roles, which simplifies software but constrains the minimum feature set per part.

Bandwidth per chip and what it implies

The generational numbers that matter are the SerDes lane rate and the aggregate switching bandwidth. A 25.6 Tb/s device driving 64 ports of 400G is one design point; the same aggregate bandwidth achieved with several smaller chips introduces extra hops, more power, and additional failure domains. Using one larger chip versus six smaller ones to build an equivalent switch is a real architectural choice with latency, thermal and resilience consequences, and it is why the highest-radix devices command a price premium that is not purely about port count.

! Questions that reveal the silicon without reading a datasheet
show platform                       ! ASIC vendor and SKU where exposed
show interface counters             ! counter granularity: per-queue or per-port only
show queue watermark                ! buffer visibility
show platform environment           ! per-chip power and temperature

Consequences that show up in production

• Buffer depth determines loss behaviour. A shallow-buffer fabric switch will drop microbursts that a deep-buffer platform absorbs. If the workload is storage or RoCEv2, this is the single most important specification and it is often the one missing from the datasheet.
• Programmability costs bandwidth. A fully programmable pipeline can implement new features in the field, but the parts that prioritise flexibility typically offer less bandwidth or deeper feature pipelines at the same power. The trade is explicit in some product lines - for example a variant that halves bandwidth and drops Layer 3 routing to double the security inspection capacity.
• Telemetry granularity is a hardware property. Streaming per-queue statistics and in-band network telemetry depend on ASIC support, so an observability strategy must be validated against the exact SKU rather than against the product family.
• Vendors using merchant silicon compensate elsewhere. When two products share the same ASIC, the differences appear in memory, table sizes, software quality and support - which is where the purchase decision actually lives.

Practical guidance: define the workload first (AI/ML fabric, storage, general enterprise access, service provider edge), then require the vendor to state buffer depth, table sizes, telemetry capabilities and power for the specific SKU. Where buffer behaviour is the deciding factor, see SmokePing latency monitoring; for the fabric design that the silicon feeds, see Nexus 9300 versus 9500 selection and 800G coherent pluggables.

原文链接：https://www.nextplatform.com/connect/2020/12/02/broadcom-widens-and-smartens-switch-chip-lineup/1650054